CROSS-CORE INVALIDATION SNAPSHOT MANAGEMENT

CROSS-CORE INVALIDATION SNAPSHOT MANAGEMENT

A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sy...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Bronson, Timothy, Giri, Akash V, Alexander, Gregory William, Berger, Deanna Postles Dunn, Branciforte, Richard Joseph, Tsai, Aaron
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sync state for at least one processor in a plurality of processors signifying that a line may have been changed by another processor since last fetched by a requesting processor.