HARDWARE ACCELERATOR FOR FLOATING-POINT OPERATIONS

A device includes integer multiplier circuits, a multiplexer circuit configured to provide portions of mantissas of a set of first data elements having a floating-point data type and portions of mantissas of a set of second data elements having the floating-point data type to respective integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product. The device further includes output circuits configured to generate an output data element based on the partial products generated by the integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements. The multiplexer circuit is further configured to bypass providing least-significant portions of the mantissas of the set of first data elements to integer multiplier circuits for multiplication with least-significant portions of the mantissas of the set of second data elements.