SEMICONDUCTOR VOID PLACEMENT

SEMICONDUCTOR VOID PLACEMENT

A method of semiconductor modelling includes determining for a virtual model of a layer of a semiconductor package, wherein the layer includes a metal layer, one or more first regions of the layer that do not satisfy a first layer design rule; adding first voids to the one or more first regions to s...

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Hauptverfasser: SNIDER, Todd, JOSHI, Prakaram, MOOLA, Srinivas
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator SNIDER, Todd
JOSHI, Prakaram
MOOLA, Srinivas
description A method of semiconductor modelling includes determining for a virtual model of a layer of a semiconductor package, wherein the layer includes a metal layer, one or more first regions of the layer that do not satisfy a first layer design rule; adding first voids to the one or more first regions to satisfy the first layer design rule; determining for the layer including the metal pattern and the first voids, one or more second regions of the layer that do not satisfy a second layer design rule, different from the first layer design rule; and adding second voids to the one or more second regions to satisfy the second layer design rule.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SEMICONDUCTOR VOID PLACEMENT
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