SEMICONDUCTOR VOID PLACEMENT

A method of semiconductor modelling includes determining for a virtual model of a layer of a semiconductor package, wherein the layer includes a metal layer, one or more first regions of the layer that do not satisfy a first layer design rule; adding first voids to the one or more first regions to satisfy the first layer design rule; determining for the layer including the metal pattern and the first voids, one or more second regions of the layer that do not satisfy a second layer design rule, different from the first layer design rule; and adding second voids to the one or more second regions to satisfy the second layer design rule.