GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP VIA SUBSTRATE CONTACTS FOR SUB-FIN ELECTRICAL CONTACT

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP VIA SUBSTRATE CONTACTS FOR SUB-FIN ELECTRICAL CONTACT

Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin pr...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KOLLURU, Kalyan, LIN, Chung-Hsun, GOLONZKA, Oleg, JACK, Nathan, GUHA, Biswajeet, HSU, William, KAR, Ayan, THOMSON, Nicholas, PHOA, Kinyip, GHANI, Tahir, ORR, Benjamin
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.