DIGITAL-TO-ANALOG CONVERTER WITH SORTING OF UNIT CELLS THAT IS BASED ON MISMATCH ERRORS AND/OR SELECTION OF NEW POINTER LOCATION THAT IS BASED ON UTILZATION RATES OF UNIT CELLS AND ASSOCIATED METHOD

A digital-to-analog converter (DAC) includes a plurality of DAC cells, a mismatch error sorting circuit, and a dynamic element matching (DEM) circuit. The mismatch error sorting circuit generates a sorting result of the plurality of DAC cells according to mismatch error levels of the plurality of DAC cells. The DEM circuit shapes the mismatch error levels of the plurality of DAC cells according to the sorting result of the plurality of DAC cells.