VIA FORMED IN A WAFER USING A FRONT-SIDE AND A BACK-SIDE PROCESS

One embodiment is a method including forming a partial through-substrate via (TSV) plug in a front side of a wafer, the partial TSV plug having a front side, a back side, and a body with a variable dimension in the body so that a largest dimension is at the back side of partial TSV plug. A cavity is...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	AGGARWAL, Ankur, Plunkett, Jeremy Matthew
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	One embodiment is a method including forming a partial through-substrate via (TSV) plug in a front side of a wafer, the partial TSV plug having a front side, a back side, and a body with a variable dimension in the body so that a largest dimension is at the back side of partial TSV plug. A cavity is etched in a back side of the wafer that exposes the back side of the partial TSV plug and a portion of a front side interconnect in a common etched cavity. A conductive material is deposited to connect the exposed portion of the front side interconnect to the back side of the wafer and to connect the exposed back side of the partial TSV plug to the back side of the wafer without connecting the partial TSV plug and the portion of the front side interconnect.