THREE-DIMENSIONAL MEMORY ARRAY WITH DUAL-LEVEL PERIPHERAL CIRCUITS AND METHODS FOR FORMING THE SAME

THREE-DIMENSIONAL MEMORY ARRAY WITH DUAL-LEVEL PERIPHERAL CIRCUITS AND METHODS FOR FORMING THE SAME

A bonded assembly includes a memory die containing a three-dimensional memory array, a first logic die bonded to the memory die, a first peripheral circuit located in the logic die and configured to control operation of a first set of electrical nodes of the three-dimensional memory array, and a sec...

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Bibliographische Detailangaben
Hauptverfasser: TOYAMA, Fumiaki, TSUTSUMI, Masanori, OGAWA, Hiroyuki, YOSHIZAWA, Kazutaka
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:A bonded assembly includes a memory die containing a three-dimensional memory array, a first logic die bonded to the memory die, a first peripheral circuit located in the logic die and configured to control operation of a first set of electrical nodes of the three-dimensional memory array, and a second peripheral circuit configured to control operation of a second set of electrical nodes of the three-dimensional memory array, where the second peripheral circuit is located at a different vertical level than the first peripheral circuit relative to the three-dimensional-memory array.