OPTIMAL MEMORY TIERING OF LARGE MEMORY SYSTEMS USING A MINIMAL NUMBER OF PROCESSORS

An information handling system includes a compute express link (CXL) multi-port controller (MPC). A first processor includes first memory modules coupled to the first processor. A second processor includes second memory modules coupled to the second processor. The CXL MPC is coupled via a first CXL port to the first processor and is coupled via a second CXL port to the second processor. The CXL MPC includes third memory modules coupled to the CXL MPC. The first memory modules, the second memory modules, and the third memory modules comprise a common cache coherency domain.