SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding la...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | CHANG, Jong-Hyeon PARK, Jum Yong JEE, Young Kun KANG, Un-Byoung |
description | A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024014177A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024014177A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024014177A13</originalsourceid><addsrcrecordid>eNrjZLAMdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1FwAwq7OToFeTo7hnj6uSuEeLgqBDv6uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMDQxNDc3NHQ2PiVAEADf8pUw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><source>esp@cenet</source><creator>CHANG, Jong-Hyeon ; PARK, Jum Yong ; JEE, Young Kun ; KANG, Un-Byoung</creator><creatorcontrib>CHANG, Jong-Hyeon ; PARK, Jum Yong ; JEE, Young Kun ; KANG, Un-Byoung</creatorcontrib><description>A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240111&DB=EPODOC&CC=US&NR=2024014177A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240111&DB=EPODOC&CC=US&NR=2024014177A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG, Jong-Hyeon</creatorcontrib><creatorcontrib>PARK, Jum Yong</creatorcontrib><creatorcontrib>JEE, Young Kun</creatorcontrib><creatorcontrib>KANG, Un-Byoung</creatorcontrib><title>SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><description>A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAMdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1FwAwq7OToFeTo7hnj6uSuEeLgqBDv6uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIxMDQxNDc3NHQ2PiVAEADf8pUw</recordid><startdate>20240111</startdate><enddate>20240111</enddate><creator>CHANG, Jong-Hyeon</creator><creator>PARK, Jum Yong</creator><creator>JEE, Young Kun</creator><creator>KANG, Un-Byoung</creator><scope>EVB</scope></search><sort><creationdate>20240111</creationdate><title>SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><author>CHANG, Jong-Hyeon ; PARK, Jum Yong ; JEE, Young Kun ; KANG, Un-Byoung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024014177A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANG, Jong-Hyeon</creatorcontrib><creatorcontrib>PARK, Jum Yong</creatorcontrib><creatorcontrib>JEE, Young Kun</creatorcontrib><creatorcontrib>KANG, Un-Byoung</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANG, Jong-Hyeon</au><au>PARK, Jum Yong</au><au>JEE, Young Kun</au><au>KANG, Un-Byoung</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME</title><date>2024-01-11</date><risdate>2024</risdate><abstract>A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2024014177A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T05%3A35%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHANG,%20Jong-Hyeon&rft.date=2024-01-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024014177A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |