CONTROLLER CACHE ARCHITETURE
An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups, and the memory controller comprises respective independent ca...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups, and the memory controller comprises respective independent caches corresponding to the plurality of channel groups. |
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