METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separa...

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Bibliographische Detailangaben
Hauptverfasser:	Anderson, Brent A, Chu, Albert M, Wang, Junli, Xie, Ruilong, Guo, Dechao, Chou, Anthony I
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.