3D Embedded Redistribution Layers for IC Substrate Packaging

Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mesch, Ryan, Hsu, Jun Chung
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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