3D Embedded Redistribution Layers for IC Substrate Packaging

Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that terminate non-stacked vias to have decreased widths or diameters without extra capture space. The redistribution layers have vias with vertical or near vertical sidewalls. Vias may also have various shapes, widths, or lengths. Traces in the redistribution layers may have various lengths and shapes with lengths that may extend into layers routing the vias to provide increased metal density in the traces.