SEMICONDUCTOR MEMORY DEVICE INCLUDING CHALCOGENIDE

A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional grad...

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Bibliographische Detailangaben
Hauptverfasser: Hwang, Uk, Ahn, Jun Ku, LEE, Jong Ho, Jung, Gwang Sun
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.