INTEGRATED CIRCUIT INCLUDING STATIC RANDOM ACCESS MEMORY DEVICE

An integrated circuit includes a static random access memory (SRAM) device. The SRAM device includes an SRAM unit cell that includes a first output node to which a first pull-up transistor, a first pull-down transistor, and a second pull-down transistor are commonly connected, and a second output node to which a second pull-up transistor, a third pull-down transistor, and a fourth pull-down transistor are commonly connected. The first output node is connected to a first gate electrode, a second gate electrode, a first connection wiring line, a first node formation pattern, and a first active contact, and a layout of the first output node, the first gate electrode, the second gate electrode, the first connection wiring line, the first node formation pattern, and the first active contact forms a first fork shape.