CHIP-TO-CHIP INTERCONNECT WITH A LAYERED COMMUNICATION ARCHITECTURE

CHIP-TO-CHIP INTERCONNECT WITH A LAYERED COMMUNICATION ARCHITECTURE

A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence proces...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Srinivasan, Arvind, Hasani, Naader, Kansal, Pankaj, Reddy, Harikrishna Madadi
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.