MULTI-TIER MEMORY STRUCTURE WITH GRADED CHARACTERISTICS

Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film t...

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Bibliographische Detailangaben
Hauptverfasser:	Lajoie, Travis W, Ferrari, Lorenzo, Le, Van H, Venkatraman, Vishak, Armstrong, Mark, Kim, Jisoo, Sultana, Afrin, Taneja, Deepyanti, Dolejsi, Moshe, Madisetti, Shailesh Kumar, Hamzaoglu, Fatih, Vo, Eva, Jen, Timothy, Sharma, Abhishek Anil, Mahmoudabadi, Forough, Zhong, Yue, Chiu, Yu-Che, Baloch, Kamal H, Evani, Vamsi, Yang, Yang, Chen, Albert B, Alzate-Vinasco, Juan G, Tan, Cheng, Reshotko, Miriam R, Kannegulla, Akash
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.