MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE

Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the...

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Hauptverfasser: Lajoie, Travis W, Chen, Albert B, Le, Van H, Venkatraman, Vishak, Armstrong, Mark, Sharma, Abhishek Anil, Sultana, Afrin, Taneja, Deepyanti, Dolejsi, Moshe, Baloch, Kamal H, Jen, Timothy, Madisetti, Shailesh Kumar
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creator Lajoie, Travis W
Chen, Albert B
Le, Van H
Venkatraman, Vishak
Armstrong, Mark
Sharma, Abhishek Anil
Sultana, Afrin
Taneja, Deepyanti
Dolejsi, Moshe
Baloch, Kamal H
Jen, Timothy
Madisetti, Shailesh Kumar
description Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023369426A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023369426A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023369426A13</originalsourceid><addsrcrecordid>eNqNyr0KwjAUQOEsDqK-wwUXHQqaSMHxkh8aSBO4uRmcSpE4iRbq-2MHH8DpwMdZC-pLYN8EvFmyBnIqpC1gNGAIfQSdIqPmDC4RIHC3mPOhByaM2Wde-MCOj5CZiuZCditWj_E5192vG7F3lnXX1Ok91Hka7_VVP0PJ8iSVaq8X2eJZ_Xd9AXz2MHI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE</title><source>esp@cenet</source><creator>Lajoie, Travis W ; Chen, Albert B ; Le, Van H ; Venkatraman, Vishak ; Armstrong, Mark ; Sharma, Abhishek Anil ; Sultana, Afrin ; Taneja, Deepyanti ; Dolejsi, Moshe ; Baloch, Kamal H ; Jen, Timothy ; Madisetti, Shailesh Kumar</creator><creatorcontrib>Lajoie, Travis W ; Chen, Albert B ; Le, Van H ; Venkatraman, Vishak ; Armstrong, Mark ; Sharma, Abhishek Anil ; Sultana, Afrin ; Taneja, Deepyanti ; Dolejsi, Moshe ; Baloch, Kamal H ; Jen, Timothy ; Madisetti, Shailesh Kumar</creatorcontrib><description>Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231116&amp;DB=EPODOC&amp;CC=US&amp;NR=2023369426A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231116&amp;DB=EPODOC&amp;CC=US&amp;NR=2023369426A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lajoie, Travis W</creatorcontrib><creatorcontrib>Chen, Albert B</creatorcontrib><creatorcontrib>Le, Van H</creatorcontrib><creatorcontrib>Venkatraman, Vishak</creatorcontrib><creatorcontrib>Armstrong, Mark</creatorcontrib><creatorcontrib>Sharma, Abhishek Anil</creatorcontrib><creatorcontrib>Sultana, Afrin</creatorcontrib><creatorcontrib>Taneja, Deepyanti</creatorcontrib><creatorcontrib>Dolejsi, Moshe</creatorcontrib><creatorcontrib>Baloch, Kamal H</creatorcontrib><creatorcontrib>Jen, Timothy</creatorcontrib><creatorcontrib>Madisetti, Shailesh Kumar</creatorcontrib><title>MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE</title><description>Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAUQOEsDqK-wwUXHQqaSMHxkh8aSBO4uRmcSpE4iRbq-2MHH8DpwMdZC-pLYN8EvFmyBnIqpC1gNGAIfQSdIqPmDC4RIHC3mPOhByaM2Wde-MCOj5CZiuZCditWj_E5192vG7F3lnXX1Ok91Hka7_VVP0PJ8iSVaq8X2eJZ_Xd9AXz2MHI</recordid><startdate>20231116</startdate><enddate>20231116</enddate><creator>Lajoie, Travis W</creator><creator>Chen, Albert B</creator><creator>Le, Van H</creator><creator>Venkatraman, Vishak</creator><creator>Armstrong, Mark</creator><creator>Sharma, Abhishek Anil</creator><creator>Sultana, Afrin</creator><creator>Taneja, Deepyanti</creator><creator>Dolejsi, Moshe</creator><creator>Baloch, Kamal H</creator><creator>Jen, Timothy</creator><creator>Madisetti, Shailesh Kumar</creator><scope>EVB</scope></search><sort><creationdate>20231116</creationdate><title>MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE</title><author>Lajoie, Travis W ; Chen, Albert B ; Le, Van H ; Venkatraman, Vishak ; Armstrong, Mark ; Sharma, Abhishek Anil ; Sultana, Afrin ; Taneja, Deepyanti ; Dolejsi, Moshe ; Baloch, Kamal H ; Jen, Timothy ; Madisetti, Shailesh Kumar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023369426A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lajoie, Travis W</creatorcontrib><creatorcontrib>Chen, Albert B</creatorcontrib><creatorcontrib>Le, Van H</creatorcontrib><creatorcontrib>Venkatraman, Vishak</creatorcontrib><creatorcontrib>Armstrong, Mark</creatorcontrib><creatorcontrib>Sharma, Abhishek Anil</creatorcontrib><creatorcontrib>Sultana, Afrin</creatorcontrib><creatorcontrib>Taneja, Deepyanti</creatorcontrib><creatorcontrib>Dolejsi, Moshe</creatorcontrib><creatorcontrib>Baloch, Kamal H</creatorcontrib><creatorcontrib>Jen, Timothy</creatorcontrib><creatorcontrib>Madisetti, Shailesh Kumar</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lajoie, Travis W</au><au>Chen, Albert B</au><au>Le, Van H</au><au>Venkatraman, Vishak</au><au>Armstrong, Mark</au><au>Sharma, Abhishek Anil</au><au>Sultana, Afrin</au><au>Taneja, Deepyanti</au><au>Dolejsi, Moshe</au><au>Baloch, Kamal H</au><au>Jen, Timothy</au><au>Madisetti, Shailesh Kumar</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE</title><date>2023-11-16</date><risdate>2023</risdate><abstract>Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T03%3A59%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lajoie,%20Travis%20W&rft.date=2023-11-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023369426A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true