POWER-EFFICIENT ACCESS LINE OPERATION FOR MEMORY

Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.