LATCH-BASED STORAGE CIRCUITS HAVING EFFICIENT INTEGRATED CIRCUIT LAYOUTS

A storage circuit includes a multi-stage latch circuit having first to fourth transistor pairs therein, which respectively include a pull-up transistor and a pull-down transistor connected in series through a corresponding one of first to fourth storage nodes. An access circuit is provided, which has a plurality of access transistors of different conductivity type therein. The access transistors are electrically coupled to at least two of the first to fourth storage nodes and configured to enable writing of data bits into at least some of the first to fourth storage nodes, and reading of data bits from at least some of the first to fourth storage nodes. A control circuit is provided, which controls the access circuit during the writing and reading.