SEMICONDUCTOR PACKAGES

In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metalli...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Chen, Wei-Yu, Huang, Li-Hsien, Su, An-Jhih, Yeh, Ming Shih, Yeh, Der-Chyang
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.