SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: JANG, Kihoon, KWON, Donghoon, YOON, Boun
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator JANG, Kihoon
KWON, Donghoon
YOON, Boun
description A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately stacked with the gate electrodes, through-insulating regions passing through the gate electrodes in a second region, a capping insulating layer covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer, channel structures passing through the capping insulating layer and the gate electrodes in a first region, upper contact plugs passing through the upper insulating layer, bit lines on the upper insulating layer, first contact plugs passing through the capping insulating layer, and conductive patterns including second contact plugs passing through each of the through-insulating regions in the second region. The conductive patterns include connection portions integral with the second contact plugs.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023328987A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023328987A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023328987A13</originalsourceid><addsrcrecordid>eNrjZLANdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNRcPVxdQ4J8vfzdFYIjgwOcfVV8PRz9gl18fRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxsZGFpYW5o6GxsSpAgDgvirj</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><source>esp@cenet</source><creator>JANG, Kihoon ; KWON, Donghoon ; YOON, Boun</creator><creatorcontrib>JANG, Kihoon ; KWON, Donghoon ; YOON, Boun</creatorcontrib><description>A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately stacked with the gate electrodes, through-insulating regions passing through the gate electrodes in a second region, a capping insulating layer covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer, channel structures passing through the capping insulating layer and the gate electrodes in a first region, upper contact plugs passing through the upper insulating layer, bit lines on the upper insulating layer, first contact plugs passing through the capping insulating layer, and conductive patterns including second contact plugs passing through each of the through-insulating regions in the second region. The conductive patterns include connection portions integral with the second contact plugs.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231012&amp;DB=EPODOC&amp;CC=US&amp;NR=2023328987A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231012&amp;DB=EPODOC&amp;CC=US&amp;NR=2023328987A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JANG, Kihoon</creatorcontrib><creatorcontrib>KWON, Donghoon</creatorcontrib><creatorcontrib>YOON, Boun</creatorcontrib><title>SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><description>A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately stacked with the gate electrodes, through-insulating regions passing through the gate electrodes in a second region, a capping insulating layer covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer, channel structures passing through the capping insulating layer and the gate electrodes in a first region, upper contact plugs passing through the upper insulating layer, bit lines on the upper insulating layer, first contact plugs passing through the capping insulating layer, and conductive patterns including second contact plugs passing through each of the through-insulating regions in the second region. The conductive patterns include connection portions integral with the second contact plugs.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLANdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNRcPVxdQ4J8vfzdFYIjgwOcfVV8PRz9gl18fRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxsZGFpYW5o6GxsSpAgDgvirj</recordid><startdate>20231012</startdate><enddate>20231012</enddate><creator>JANG, Kihoon</creator><creator>KWON, Donghoon</creator><creator>YOON, Boun</creator><scope>EVB</scope></search><sort><creationdate>20231012</creationdate><title>SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><author>JANG, Kihoon ; KWON, Donghoon ; YOON, Boun</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023328987A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JANG, Kihoon</creatorcontrib><creatorcontrib>KWON, Donghoon</creatorcontrib><creatorcontrib>YOON, Boun</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JANG, Kihoon</au><au>KWON, Donghoon</au><au>YOON, Boun</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME</title><date>2023-10-12</date><risdate>2023</risdate><abstract>A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately stacked with the gate electrodes, through-insulating regions passing through the gate electrodes in a second region, a capping insulating layer covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer, channel structures passing through the capping insulating layer and the gate electrodes in a first region, upper contact plugs passing through the upper insulating layer, bit lines on the upper insulating layer, first contact plugs passing through the capping insulating layer, and conductive patterns including second contact plugs passing through each of the through-insulating regions in the second region. The conductive patterns include connection portions integral with the second contact plugs.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2023328987A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T14%3A27%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JANG,%20Kihoon&rft.date=2023-10-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023328987A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true