MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS

MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell arr...

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Bibliographische Detailangaben
Hauptverfasser: KUMAZAKI, Noriyasu, SHIBAZAKI, Yuzuru, SANAD, Bushnaq, SATO, Junichi, TERADA, Yuri, UEHARA, Kazuto, ASAOKA, Norichika, HANDA, Takaya, YAMAOKA, Masashi, ISOMURA, Ryosuke, SUGAHARA, Akio
Format: Patent
Sprache:eng
Schlagworte:
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.