Transistor And Methods Of Forming Integrated Circuitry

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and...

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Bibliographische Detailangaben
Hauptverfasser: Hull, Jeffery B, Chhajed, Sameer, Liu, Hung-Wei, Khandekar, Anish A
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.