TECHNIQUES, DEVICES, AND INSTRUCTION SET ARCHITECTURE FOR BALANCED AND SECURE LADDER COMPUTATIONS

TECHNIQUES, DEVICES, AND INSTRUCTION SET ARCHITECTURE FOR BALANCED AND SECURE LADDER COMPUTATIONS

Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments balance execution of various iterations in a way that is balanced for different sec...

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Bibliographische Detailangaben
Hauptverfasser: Yao, Chen, Qian, Yuji, Pan, Weiping, Xie, Xixi, Wu, Xiao, Wang, Shuai, Zhu, Rongzhe, Yang, Kun
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Zusammenfassung:Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments balance execution of various iterations in a way that is balanced for different secret values, significantly reducing vulnerability of ladder computations to adversarial side-channel attacks.