MEMORY CONTROLLER ZERO CACHE

In one embodiment, a controller in a microprocessor, the controller configured to manage accesses to dynamic random access memory (DRAM), the controller comprising: a first table configured to track cache lines that have been written to zero for a plurality of first memory regions; and a second table configured to track the cache lines that have been written to zero for a plurality of second memory regions, wherein each of the plurality of second memory regions comprises a group of the plurality of first memory regions where all of the cache lines within each of the plurality of the first memory regions within the group have been written to zero.