ZERO BITS IN L3 TAGS

In one embodiment, a microprocessor, comprising: plural cores, each of the cores comprising a level 1 (L1) cache and a level 2 (L2) cache; and a shared level 3 (L3) cache comprising plural L3 tag array entries, wherein a first portion of the plural L3 tag array entries is associated with data and a second portion of the plural L3 tag array entries is decoupled from data, wherein each L3 tag array entry comprises tag information and data zero information, the data zero information indicating whether any data associated with the tag information is known to be zero or not.