HIGH-BANDWIDTH POWER ESTIMATOR FOR AI ACCELERATOR

A processor IC has multiple power base units (PBUs), arranged in an array. Each PBU includes a switch, a memory unit and a compute unit. It further includes a power estimator for the switch, memory unit, and compute unit. The PBUs communicate with an array-level power accumulator via dedicated wiring. Communication via the dedicated wiring may use timestamps to ensure time-accurate aggregate estimates. The switch power estimator estimates dissipation based on port activity. The memory power estimator estimates dissipation based on read and write activity and bit toggling in the memory. The compute power estimator estimates power based on monitoring input data zero values, bit toggling, instruction type, and activity of reconfigurable processing units. The array-level power accumulator calculates the array-level nominal dynamic power estimate. A power clock management controller scales the dynamic power estimate for the actual clock frequency and measured supply voltage, and adds a static power estimate.