SCALED QUANTUM CIRCUITS

Techniques for forming respective groups of quantum circuit elements (QCEs) on respective crystalline surfaces of a crystalline dielectric (CD) layer are presented. Vias can be formed in the CD layer. Second QCEs can be formed on a second crystalline surface of the CD layer. A seal layer can be applied to the patterned second metallization layer that forms the second QCEs. A handle wafer can be bonded to the seal layer. The chip stack can be turned over to place a substrate at the top, and handle wafer at the bottom, of the chip stack. The substrate and a buried oxide layer can be removed to expose the first crystalline surface of the CD layer. First QCEs can be formed on the first crystalline surface of the CD layer. A portion of the first QCEs can be coupled or interconnected to a portion of the second QCEs.