FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SCALING OF GATE-ALL-AROUND TRANSISTORS

FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SCALING OF GATE-ALL-AROUND TRANSISTORS

Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately fo...

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Bibliographische Detailangaben
Hauptverfasser: Das, Ritesh, Hasan, Mohammad, Thirtha, Vivek, Golonzka, Oleg, Kumar, Nitesh, Guha, Biswajeet, Hsu, William
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.