PROCESSOR CHIP TIMING ADJUSTMENT ENHANCEMENT

PROCESSOR CHIP TIMING ADJUSTMENT ENHANCEMENT

Data relating to one or more circuit paths may be collected during a design stage of a processor chip based on a design model. One or more delta values may be added to the one or more circuit paths of the design model. One or more broken circuit paths may be identified based on the one or more delta...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHRISTENSEN, TODD A, PETERSON, KIRK D, SHEETS, II, JOHN E, MARZ, ERIC
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Data relating to one or more circuit paths may be collected during a design stage of a processor chip based on a design model. One or more delta values may be added to the one or more circuit paths of the design model. One or more broken circuit paths may be identified based on the one or more delta values. A target time for each of the one or more broken circuit paths may be adjusted.