INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via...

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Hauptverfasser: AHN, Jeong Hoon, JANG, Woo Seong, HWANG, Je Gwan, KIM, Ji Hyung, HONG, Seok Jun, PARK, Won Ji, OH, Jae Hee, DING, Shaofeng
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creator AHN, Jeong Hoon
JANG, Woo Seong
HWANG, Je Gwan
KIM, Ji Hyung
HONG, Seok Jun
PARK, Won Ji
OH, Jae Hee
DING, Shaofeng
description An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023170289A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023170289A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023170289A13</originalsourceid><addsrcrecordid>eNrjZHD09AtxDQrwD3YNUggOCQp1DgkNclVw9HNRCHb19XT293MBCvkHKQQ4Ons7ursqePo5-4S6ePq5K4R4uCoEO_q68jCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSS-NBgIwMjY0NzAyMLS0dDY-JUAQCtSSwe</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME</title><source>esp@cenet</source><creator>AHN, Jeong Hoon ; JANG, Woo Seong ; HWANG, Je Gwan ; KIM, Ji Hyung ; HONG, Seok Jun ; PARK, Won Ji ; OH, Jae Hee ; DING, Shaofeng</creator><creatorcontrib>AHN, Jeong Hoon ; JANG, Woo Seong ; HWANG, Je Gwan ; KIM, Ji Hyung ; HONG, Seok Jun ; PARK, Won Ji ; OH, Jae Hee ; DING, Shaofeng</creatorcontrib><description>An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230601&amp;DB=EPODOC&amp;CC=US&amp;NR=2023170289A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230601&amp;DB=EPODOC&amp;CC=US&amp;NR=2023170289A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AHN, Jeong Hoon</creatorcontrib><creatorcontrib>JANG, Woo Seong</creatorcontrib><creatorcontrib>HWANG, Je Gwan</creatorcontrib><creatorcontrib>KIM, Ji Hyung</creatorcontrib><creatorcontrib>HONG, Seok Jun</creatorcontrib><creatorcontrib>PARK, Won Ji</creatorcontrib><creatorcontrib>OH, Jae Hee</creatorcontrib><creatorcontrib>DING, Shaofeng</creatorcontrib><title>INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME</title><description>An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD09AtxDQrwD3YNUggOCQp1DgkNclVw9HNRCHb19XT293MBCvkHKQQ4Ons7ursqePo5-4S6ePq5K4R4uCoEO_q68jCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSS-NBgIwMjY0NzAyMLS0dDY-JUAQCtSSwe</recordid><startdate>20230601</startdate><enddate>20230601</enddate><creator>AHN, Jeong Hoon</creator><creator>JANG, Woo Seong</creator><creator>HWANG, Je Gwan</creator><creator>KIM, Ji Hyung</creator><creator>HONG, Seok Jun</creator><creator>PARK, Won Ji</creator><creator>OH, Jae Hee</creator><creator>DING, Shaofeng</creator><scope>EVB</scope></search><sort><creationdate>20230601</creationdate><title>INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME</title><author>AHN, Jeong Hoon ; JANG, Woo Seong ; HWANG, Je Gwan ; KIM, Ji Hyung ; HONG, Seok Jun ; PARK, Won Ji ; OH, Jae Hee ; DING, Shaofeng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023170289A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AHN, Jeong Hoon</creatorcontrib><creatorcontrib>JANG, Woo Seong</creatorcontrib><creatorcontrib>HWANG, Je Gwan</creatorcontrib><creatorcontrib>KIM, Ji Hyung</creatorcontrib><creatorcontrib>HONG, Seok Jun</creatorcontrib><creatorcontrib>PARK, Won Ji</creatorcontrib><creatorcontrib>OH, Jae Hee</creatorcontrib><creatorcontrib>DING, Shaofeng</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AHN, Jeong Hoon</au><au>JANG, Woo Seong</au><au>HWANG, Je Gwan</au><au>KIM, Ji Hyung</au><au>HONG, Seok Jun</au><au>PARK, Won Ji</au><au>OH, Jae Hee</au><au>DING, Shaofeng</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME</title><date>2023-06-01</date><risdate>2023</risdate><abstract>An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title INTERPOSER STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T18%3A13%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AHN,%20Jeong%20Hoon&rft.date=2023-06-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023170289A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true