MEMORY DEVICE

A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.