STACKED FIELD-EFFECT TRANSISTORS WITH A SHIELDED OUTPUT

Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.