Low Power Memory System Using Dual Input-Output Voltage Supplies

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage...

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Bibliographische Detailangaben
Hauptverfasser: PARK, Joon Young, SUH, Jungwon, NAGARAJAN, Mahalingam
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.