PACKAGING ARCHITECTURES FOR SUB-TERAHERTZ RADIO FREQUENCY DEVICES

A microelectronic assembly is provided comprising: a first IC die in a first layer comprising an array of radio frequency (RF) patch antennas on a side opposite to a second layer; a second IC die in the second layer between the first layer and a third layer; and a third IC die in the third layer. The first IC die comprises RF and analog circuitry, the first IC die is part of an array of IC dies having similar size and circuitry as the first IC die, the second layer and the third layer comprise a dielectric with through-dielectric vias (TDVs) therein surrounding the second IC die and the third IC die, respectively, and an interface between adjacent layers comprises interconnects having a pitch of 10 micrometers between adjacent interconnects.