DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data proce...
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| creator | Tuan, Tim Vissers, Kornelis A Langer, Jan Ozgul, Baris Walke, Richard L Clarke, David Noguera Serra, Juan J Bilski, Goran HK Wittig, Ralph D |
| description | A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023131698A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023131698A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023131698A13</originalsourceid><addsrcrecordid>eNrjZNBzcQxxVAgI8nd2DQ729HNXcPVz9_RzVXAMCnL0c3f1dfULUfD0U3BUcHEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxobGhmaWFo6GxsSpAgBV2iZY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE</title><source>esp@cenet</source><creator>Tuan, Tim ; Vissers, Kornelis A ; Langer, Jan ; Ozgul, Baris ; Walke, Richard L ; Clarke, David ; Noguera Serra, Juan J ; Bilski, Goran HK ; Wittig, Ralph D</creator><creatorcontrib>Tuan, Tim ; Vissers, Kornelis A ; Langer, Jan ; Ozgul, Baris ; Walke, Richard L ; Clarke, David ; Noguera Serra, Juan J ; Bilski, Goran HK ; Wittig, Ralph D</creatorcontrib><description>A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230427&DB=EPODOC&CC=US&NR=2023131698A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230427&DB=EPODOC&CC=US&NR=2023131698A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tuan, Tim</creatorcontrib><creatorcontrib>Vissers, Kornelis A</creatorcontrib><creatorcontrib>Langer, Jan</creatorcontrib><creatorcontrib>Ozgul, Baris</creatorcontrib><creatorcontrib>Walke, Richard L</creatorcontrib><creatorcontrib>Clarke, David</creatorcontrib><creatorcontrib>Noguera Serra, Juan J</creatorcontrib><creatorcontrib>Bilski, Goran HK</creatorcontrib><creatorcontrib>Wittig, Ralph D</creatorcontrib><title>DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE</title><description>A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBzcQxxVAgI8nd2DQ729HNXcPVz9_RzVXAMCnL0c3f1dfULUfD0U3BUcHEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxobGhmaWFo6GxsSpAgBV2iZY</recordid><startdate>20230427</startdate><enddate>20230427</enddate><creator>Tuan, Tim</creator><creator>Vissers, Kornelis A</creator><creator>Langer, Jan</creator><creator>Ozgul, Baris</creator><creator>Walke, Richard L</creator><creator>Clarke, David</creator><creator>Noguera Serra, Juan J</creator><creator>Bilski, Goran HK</creator><creator>Wittig, Ralph D</creator><scope>EVB</scope></search><sort><creationdate>20230427</creationdate><title>DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE</title><author>Tuan, Tim ; Vissers, Kornelis A ; Langer, Jan ; Ozgul, Baris ; Walke, Richard L ; Clarke, David ; Noguera Serra, Juan J ; Bilski, Goran HK ; Wittig, Ralph D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023131698A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Tuan, Tim</creatorcontrib><creatorcontrib>Vissers, Kornelis A</creatorcontrib><creatorcontrib>Langer, Jan</creatorcontrib><creatorcontrib>Ozgul, Baris</creatorcontrib><creatorcontrib>Walke, Richard L</creatorcontrib><creatorcontrib>Clarke, David</creatorcontrib><creatorcontrib>Noguera Serra, Juan J</creatorcontrib><creatorcontrib>Bilski, Goran HK</creatorcontrib><creatorcontrib>Wittig, Ralph D</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tuan, Tim</au><au>Vissers, Kornelis A</au><au>Langer, Jan</au><au>Ozgul, Baris</au><au>Walke, Richard L</au><au>Clarke, David</au><au>Noguera Serra, Juan J</au><au>Bilski, Goran HK</au><au>Wittig, Ralph D</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE</title><date>2023-04-27</date><risdate>2023</risdate><abstract>A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE |
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