TEST METHOD

Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned insp...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TATEMICHI, Shuhei, ISHII, Kenichi
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned inspection voltage to the semiconductor devices for setting, and testing, at a first temperature, the plurality of semiconductor devices for setting included in each of the plurality of groups for setting; performing second testing by testing, at a second temperature different from the first temperature, a semiconductor device for setting having been determined as being non-defective and by detecting a breakdown voltage at which the semiconductor device for setting is broken; acquiring a relationship between the inspection voltage and the breakdown voltage; and setting an applied voltage used when testing a semiconductor device under test at the first temperature, based on the acquired relationship.