PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING

An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	YEN, Ting-Ta, SMEYS, Peter
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TRANSPORTING
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Beschreibung
Zusammenfassung:	An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to the surface and a bond pad on the surface and coupled to the device. The cap wafer is bonded to the device substrate and partially diced at the first and second dicing grooves such that the bond pad is exposed. Aligning the cap wafer and the device substrate includes aligning the first and second dicing grooves between the bond pad and a bonding area at which the cap wafer is bonded to the device substrate. A width of the first and second dicing grooves prevents cap wafer dust formed during the partial dicing from falling on the bond pad.