MULTIPLE SPACER PATTERNING SCHEMES
The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A...
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| creator | OSHIO, Hidetaka LI, Chao LIN, Yung-chen JANAKIRAMAN, Karthik GUGGILLA, Srinivas CHENG, Rui KEDLAYA, Diwakar GUPTA, Meenakshi YANG, Tzu-shun HUANG, Zubin LEE, Gene |
| description | The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer. |
| format | Patent |
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In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230323&DB=EPODOC&CC=US&NR=2023093450A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230323&DB=EPODOC&CC=US&NR=2023093450A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OSHIO, Hidetaka</creatorcontrib><creatorcontrib>LI, Chao</creatorcontrib><creatorcontrib>LIN, Yung-chen</creatorcontrib><creatorcontrib>JANAKIRAMAN, Karthik</creatorcontrib><creatorcontrib>GUGGILLA, Srinivas</creatorcontrib><creatorcontrib>CHENG, Rui</creatorcontrib><creatorcontrib>KEDLAYA, Diwakar</creatorcontrib><creatorcontrib>GUPTA, Meenakshi</creatorcontrib><creatorcontrib>YANG, Tzu-shun</creatorcontrib><creatorcontrib>HUANG, Zubin</creatorcontrib><creatorcontrib>LEE, Gene</creatorcontrib><title>MULTIPLE SPACER PATTERNING SCHEMES</title><description>The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. 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A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDyDfUJ8QzwcVUIDnB0dg1SCHAMCXEN8vP0c1cIdvZw9XUN5mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGxgaWxiamBo6GxsSpAgDUxyOD</recordid><startdate>20230323</startdate><enddate>20230323</enddate><creator>OSHIO, Hidetaka</creator><creator>LI, Chao</creator><creator>LIN, Yung-chen</creator><creator>JANAKIRAMAN, Karthik</creator><creator>GUGGILLA, Srinivas</creator><creator>CHENG, Rui</creator><creator>KEDLAYA, Diwakar</creator><creator>GUPTA, Meenakshi</creator><creator>YANG, Tzu-shun</creator><creator>HUANG, Zubin</creator><creator>LEE, Gene</creator><scope>EVB</scope></search><sort><creationdate>20230323</creationdate><title>MULTIPLE SPACER PATTERNING SCHEMES</title><author>OSHIO, Hidetaka ; LI, Chao ; LIN, Yung-chen ; JANAKIRAMAN, Karthik ; GUGGILLA, Srinivas ; CHENG, Rui ; KEDLAYA, Diwakar ; GUPTA, Meenakshi ; YANG, Tzu-shun ; HUANG, Zubin ; LEE, Gene</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023093450A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OSHIO, Hidetaka</creatorcontrib><creatorcontrib>LI, Chao</creatorcontrib><creatorcontrib>LIN, Yung-chen</creatorcontrib><creatorcontrib>JANAKIRAMAN, Karthik</creatorcontrib><creatorcontrib>GUGGILLA, Srinivas</creatorcontrib><creatorcontrib>CHENG, Rui</creatorcontrib><creatorcontrib>KEDLAYA, Diwakar</creatorcontrib><creatorcontrib>GUPTA, Meenakshi</creatorcontrib><creatorcontrib>YANG, Tzu-shun</creatorcontrib><creatorcontrib>HUANG, Zubin</creatorcontrib><creatorcontrib>LEE, Gene</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OSHIO, Hidetaka</au><au>LI, Chao</au><au>LIN, Yung-chen</au><au>JANAKIRAMAN, Karthik</au><au>GUGGILLA, Srinivas</au><au>CHENG, Rui</au><au>KEDLAYA, Diwakar</au><au>GUPTA, Meenakshi</au><au>YANG, Tzu-shun</au><au>HUANG, Zubin</au><au>LEE, Gene</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTIPLE SPACER PATTERNING SCHEMES</title><date>2023-03-23</date><risdate>2023</risdate><abstract>The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | MULTIPLE SPACER PATTERNING SCHEMES |
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