MULTIPLE SPACER PATTERNING SCHEMES

MULTIPLE SPACER PATTERNING SCHEMES

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A...

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Bibliographische Detailangaben
Hauptverfasser: OSHIO, Hidetaka, LI, Chao, LIN, Yung-chen, JANAKIRAMAN, Karthik, GUGGILLA, Srinivas, CHENG, Rui, KEDLAYA, Diwakar, GUPTA, Meenakshi, YANG, Tzu-shun, HUANG, Zubin, LEE, Gene
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.