REDUCING MEMORY POWER USAGE IN FAR MEMORY

Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsi...

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Bibliographische Detailangaben
Hauptverfasser: Rubinstein, Asaf, Aqrabawi, Leo, Mukker, Anoop, Greenfield, Zvika, Gihon, Arik, Kuo, Chia-Hung S, Gandiga Shivakumar, Deepak
Format: Patent
Sprache:eng
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Zusammenfassung:Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.