VERIFIABLE MACHINE CODE
Aspects and features include a structure for a program directed to a target computing device and metadata that can be used by a verifier in the target computing device. The verifier can quickly and efficiently apply verification rules to identified sections of the program to determine whether the pr...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | Aspects and features include a structure for a program directed to a target computing device and metadata that can be used by a verifier in the target computing device. The verifier can quickly and efficiently apply verification rules to identified sections of the program to determine whether the program is safe to execute by the target computing device. In some examples, the target computing device uses the verifier to identify, using the metadata, verifiable sections of instructions that violate execution safety policies. The verifier can apply verification rules to the verifiable sections to determine whether to execute each verifiable section despite instructions in the verifiable section violating execution safety policies. The program and the metadata can be generated, as an example, by a compiler from source code, and transmitted or otherwise distributed to target computing devices. |
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