STAGGERED WORD LINE ARCHITECTURE FOR REDUCED DISTURB IN 3-DIMENSIONAL NOR MEMORY ARRAYS

A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line-which are staggered relative to the memory cells on the first side-are connected to global word lines above the memory structure.