SEMICONDUCTOR DEVICE AND SEMICONDUTOR DEVCE EXAMINATION METHOD

A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chain...

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Bibliographische Detailangaben
Hauptverfasser:	MIYAMAE, Tsutomu, FUKUDA, Nariyuki, MISHIMA, Keitarou, HOSAKA, Kazuhito, KIMURA, Koichi, YAMAGUCHI, Takeshi, OOIGAWA, Isao, TAHARA, Suguru, SANUKI, Yuichiro
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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Beschreibung
Zusammenfassung:	A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.