HIGH FREQUENCY AC COUPLED SELF-BIASED DIVIDER

Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wav...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WU, Ann Chen, KESSELRING, Grant P, STROM, James, DAVIES, Andrew D
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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