HIGH FREQUENCY AC COUPLED SELF-BIASED DIVIDER

Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.