CORRELATED ELECTRON RESISTIVE MEMORY DEVICE AND INTEGRATION SCHEMES

CORRELATED ELECTRON RESISTIVE MEMORY DEVICE AND INTEGRATION SCHEMES

A resistive memory device is provided. The resistive memory device comprises a first metal oxide layer above a body electrode. A correlated electron layer located between a source and a drain and above the first metal oxide layer. A gate above a bottom portion of the correlated electron layer.

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Bibliographische Detailangaben
Hauptverfasser: TAN, JUAN BOON, HSU, WEI-HUI, YI, WANBING, HSIEH, CURTIS CHUN-I
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A resistive memory device is provided. The resistive memory device comprises a first metal oxide layer above a body electrode. A correlated electron layer located between a source and a drain and above the first metal oxide layer. A gate above a bottom portion of the correlated electron layer.