MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDENT ON STORED DATA CONTENT

A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.